Design and simulation of digital down converter using FPGA
Abstract : The aim of this thesis is to design and implement Digital Down Converter (DDC) using Field Programmable Gate Array (FPGA) chip for input sampling frequency of 40 MHz and 25 KHz channel bandwidth. The Xilinx FPGA is chosen here with Virtex-II device to achieve this task for the DDC system implementation. The individual components of the DDC system are the mixer with its adder/subtractor and multiplier, Numerical Controlled Oscillator (NCO), and decimation filter. These components are software implemented using VHDL language, with the software called ModelSim version SE-EE 5.4a.