Field-Programmable Gate Arrays (FPGAs) have recently become a viable alternative to Application-Specific Integrated Circuits for implementing digital systems. FPGAs are programmable logic devices which can be programmed entirely by the customer and therefore offer a quick and simple way to realize circuits. The project aims to reduce the size of an on-board computer to a single chip facilitating further miniaturization of small satellites. The thesis is concerned with a telemetry communication system, specifically designed to meet the needs of a single-chip onboard computer. The main requirements were to provide a simplification of the main CCSDS TM protocol avoiding long implementation time and •cost. The development of the CCSDS software package is based on the CCSDS TM Recommendation documents, which contain the detailed specifications of the logic required to achieve a CCSDS reliable communication system. The thesis presents a VHDL model for Packet Telemetry Encoder (PTME) system which can be configured to support one up to eight Virtual Channels (VCs), one Virtual Channel Multiplexer (VCM) and a Reed Solomon Encoder (RSE) for encoding the output telemetry frame according to the CCSDS channel coding standards. Two types of input interfaces are used for the Virtual Channels supporting Packet Asynchronous (PA) and Packet Parallel (PP). The thesis also presents an implementation comparison of the PTME VHDL model using two different Xilinx's Families (Spartan and Virtex), the implementation results presented for two PTME models with model-1 four VCs, VCM and RSE, and model-2 eight VCs, VCM, RSE. All the PTME VHDL models are verified and synthesized using Xilinx Foundation 2.1i. Three different chips are tested with model-1 which were Xilinx SpartanXL, Virtex, and Spartan2. And two different chips are tested with model-2 which were Virtex and Virtex-E chips. Maximum operating clock frequency achieved by using Xilinx Virtex (XCV50BG256) chip for model-1 which was 175MHz, using 40372 system gates and utilizing 56% of the chip, while for model-2 by using Virtex-E family (XCV1000EBG560) the maximum operating frequency is 214MHz, using 401372 system gates and utilizing 25% of the chip .