Design and implementation of direct sequence FPGA-based acquisition and tracking systems.

Sefwan Subhi Hussain
Dr. Samir S. Al-Attar

Abstract : One of the most popular techniques now a day for data spreading is Direct Sequence Spread spectrum (DSSS). The data that is to be wireless ransmitted is multiplied with a high frequency pseudo-random noise (PN) sequence at the transmitter. The work in this thesis presents the design, simulation, implementation and testing of a direct sequence spread spectrum receiver. The receiver employs a Binary-Phase-Shift Keying (BPSK) signaling scheme. The basic theory of code acquisition with different techniques and structures used to achieve the initial synchronization in direct sequence spread spectrum system are discussed. The effect of noise, carrier Doppler and multi-path propagation, on system performance are simulated. Serial search scheme is used for code acquisition and tracking, and a double threshold detection scheme of receiver performance are presented and compared with traditional serial search algorithm. A modified double-dwell serial search scheme is used for code acquisition and tracking. This modified technique attempts to expect the acquisition in advance in order to reduce the time needed for the acquisition, and to reduce the time needed for reacquiring when missing the acquisition process. An average loop filter for 6 samples was used which supply the error signal for voltage control oscillator in order to smooth the tracking process. The carrier-phase is assumed to be in synchronization. Measurements for the receiver performance are presented and compared with theoretical calculations. The assessment is based on the simulation results obtained from the Matlab s simulink and FPGA software for the spread spectrum systems. Matched filter acquisition behavior was studied and compared with the serial search in a variety of scenarios; all proposed systems were studied in their cost, delay and suitability for implementation in the FPGA technology. The modified proposed system applied circuit that will check the output of the integrator at the mid period for each trial of searching rather than checking for the whole sequence using the same correlator, and decide whether to carry on or restart again. The synchronized systems have been designed in the baseband modeling then simulated and implemented using the FPGA technology. The FPGA family used for this implementation was Vertix family due to their sophisticate specification include in this family. Each part of the implementation process was done individually in order to study the cost effect for that part for the reduction processes. With this approach, system complexity resides solely in the receiver allowing the transmitter to be very small and cheap. The given simulation results and the reports by the implementation of the FPGA shown that the high speed acquisition needs a high cost for implementation.