The growth of Ethernet from 10 Mbit/s to 40 Gbit/s has surpassed the growth of microprocessor performance in mainstream servers and computers. As a result, the TCP/IP(Transmission Control Protocol/Internet Protocol) processing has become a bottleneck. Traditional software-based TCP/IP processing on general purpose processors (GPPs) is no longer able to keep pace with network wire speeds. The main reason for the bottleneck is the TCP/IP stack being processed at a rate less than the network speed, which requires offloading the processing of TCP/IP protocols from the host processor to the hardware on the adapter or in the system. The IGMP(Internet Group Management Protocol) is a simple protocol for the support of IP multicast IGMP operates between an edge router and the hosts directly connected to that router. IGMP is used by multicast routers to keep track of membership in a multicast group. It is used by IP hosts to report their host group memberships to any immediately neighboring multicast routers. This work resolves a part of the bottleneck by using TOE (TCP/IP Offload Engine) technology with FPGA (Field Programmable Gate Array) to implement IGMP processing unit that offloads the processing of IGMP protocol from the host processor to the hardware on the adapter or in the system. IGMP (version 1 and version 2) processing unit is designed in hardware, to do this the IGMP is partitioned into four modules (group-joining module, group leaving module, input module and output module), also a group table and set of timers are designed to complete the function of the modules. The four modules were described as a VHDL language using modelsim program and to explore the synthesis possibility of the VHDL program, a FPGA Spartan 3E starter kit is used to be the implementation target of the design.