With the wide growth of digital devices, it has become a vital subject to design and implements a hardware debugging tools. One of these important tools is the logic analyzer. The aim of this thesis is to design and implement a PC based logic analyzer, which is an instrument, used to debug operation of digital devices. The developed logic analyzer has 16 input channels, with a memory depth of 4K snapshots/channel. The design was made to achieve programmability in a way that the analyzer parameters can be configured manually. Parameters such as (internal or external trigger source), (falling or raising edge capture clock), (state or timing measuring mode), and also the number of pre-trigger and post-trigger snapshots can be determined by the user according to this feature. The implementation consists of two parts: the hardware part: - Involves the ISA card that does the capturing of 16 input channels and stores the snapshot on an on-board SRAM. And the software part: - Involves the kernel mode driver and the GUI program. The software part is responsible for managing the hardware card operation, configuring the analyzer as required, and displaying the captured snapshot to the user in a proper form.The system was tested to work properly in various configuration schemes. The state measurement type was verified by connecting the logic analyzer to an 8085-SDK while the timing measurement type was verified by connecting the logic analyzer to a 16-bit counter. The captured signals in all tests after being compared with theoretical results proved that the logic analyzer is working properly.