This thesis introduces the design and the hardware architecture requirements for a baseband multi-rate coded adaptive OFDM transmitter and receiver system on FPGA chip using Verilog HDL. The adaptive system depends on the number of the received frame losses by using simple CRC-12 unit to change the transmission rate. The designedsystem includes data scrambling module, error detection/correction modules, mapping modules and feedback link. The designed scrambling and error detection/correction modules are based on IEEE 802.1 la Std.Mapping modules include (QPSK, 16QAM, 64QAM and 256QAM) and finally a 64- point FFT and IFFT modules were provided by Xilinx FFT core. All modules are designed using Verilog HDL programming language, simulated and synthesized using ISE software thus, can be implemented on Xilinx Vitrtex5 FPGA chip. The system was simulated in AWGN channel with different SNR values, the results were verified based on the results obtained in MATLAB simulation. The designed system was successfully synthesized to occupy two Xilinx Virtex-5 FPGA resources, one for transmitter system and the other one for receiver system. Synthesis report shows that the system uses total hardware resources of 126 flip-flops for the transmitter system and 387 flip-flops for the receiver system. The input data can be modulated at data rate up to 120 Mbits/s..