Abstract: Programmable logic devices have replaced application specific integrated circuitsin many Applications due to lower cost, shorter time to market and hardware reconfigurability. Corresponding to this system on a programmable chip design has emerged as a major enabling technology. The implementation of satellite onboard data handling as a system on chip by the use of programmable devices will result in radical improvements and new capability. Reduction of size, complexity, and cost are benefits of such design.This work attempts to design and simulate an down-link (Telemetry) and an uplink (Telecommand) system on FPGA chip using verilog HDL, with reference to the Consultative committee for space data system (CCSDS) protocols, The design of the Telemetry Encoder includes four virtual channels followed by a virtual channel multiplexer, While Telemetry decoder have eight virtual channels, that enable the received data to demultiplexed into eight on-board data sinks. In designing Telecommand encoder/decoder, single virtual channel has been used, followed by virtual channel multiplexer. Reed-Solomon encoding technique used in telemetry system design provide both error detection and correction (as recommended by CCSDS), while CRC encoding technique provide only error detection have been used in Telecommand system, in order to ensure receiving the correct command from earth station. All modules are designed using Verilog HDL programming language, simulated and synthesized using ISE software thus, can be implemented on Xilinx Vertex FPGA family and Xilinx Spartan FPGA family. Synthesize report show that Telemetry Encoder use totally hardware resources of 34% from FPGA flip flops with clock rate 120.5 MHz using Vertex-E FPGA, and 3% from FPGA flip flop with clock rate 231.37 MHz using Spartan XL FPGA, for Telemetry Decoder 56% from FPGA flip flop with clock rate 79.145 using Vertex-E FPGA, and 4% from FPGA flip flops with clock rate 249 MHz using Spartan XL FPGA, for Telecommand Encoder 11% from FPGA flip flops with clock rate 120.5 MHz using Vertex-E FPGA, and 2% from FPGA flip flop with clock rate 377 MHz using Spartan XL FPGA, and for Telecommand Decoder use 79% from FPGA flip flops with clock rate 79 MHz using Vertex-E FPGA, and 4% from FPGA flip flop with clock rate 282 MHz using Spartan XL FPGA. Changing the coding technique from integer counter to simple shift register direct reduces the occupied resources in the FPGA chip by 24.5% The implementation shows the ability to have a complete design on a single chip that can result in lower size, less power, and more reliable implementation design.