D.C. Modeling of a partially depleted SOI MOSFET for deep submicron Technology

number: 
674
English
Degree: 
Author: 
Sameer Sami Al-Aubaidi
Supervisor: 
Dr. Ali A. Ati
Dr. Mazin A. Kadhim
year: 
2002
Abstract:

The SOI MOSFET (Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor) is formed by placing an oxide layer in Silicon substrate of Bulk MOSFET. This oxide layer will increase the speed of the transistor by reducing the Drain/Source junction capacitance's in depletion region of the transistor, and also increasing the self-heating in the transistor that cause decreasing in drain current for small channel lengths. The SOI MOSFET divided in two general types: Partially depleted (PD) and Fully depleted (FD), each type valid for D.C, A.C and transient. The present work discusses the D.C PD SOI MOSFET modeling aspects. A proposed D.C model for the PD SOI MOSFET valid for submicron technologies has been developed. The model covers the most important effects in the state of the art submicron PD SOI MOSFET, likes mobility reduction, velocity saturation, substrate current, Self-heating, floating body and kink effect. The model also characterized by using one drain current equation to describe the whole characteristics of the device over different region of operation. The correct physical treatment through the development of the model is reflected through the reasonable accuracy that the model shows when it is compared with the experimental data for PD SOI MOSFET, having different channel dimensions within the submicron range. The model expected to be the first approach for a universal PD SOI MOSFET model covering the D.C. A.C and transient analyses.