An Electronic Warfare (EW) receiver is the first part in an EW system which is responsible for detecting radar signals, analyzing them to identify the type of threat, and coordinating the operation of producing jamming signals to weaken these threats and reduce their effect in air battles. Two architectures for an EW receiver are proposed, designed, simulated using MATLAB SIMULINK and implemented using FPGAs with the Xilinx foundation 2.1i software tools. The systems analyze a 32 MHz wide band and should operate in real time. The first one is called Strongest Signal Detection Architecture (SSDA). It finds the pulse width, pulse starting time (with a 0.25 sμresolution) and frequency of the strongest received pulse (with 1 MHz resolution) and it should be used when one important pulse is expected. The second is called All Signals Power Architecture (ASPA) which produces the relative intensity for all possible signals in the covered band without the further analysis of pulse width and pulse starting time. The simulation of the two architectures proves their ability to perform the required analysis in real time. The response of both systems to three types of test signals shows correct identification for frequency of applied pulses as well as the ability to operate in real time. The systems are implemented using FPGAs. The Xilinx Virtex family of chips was used with the target device XCV1000FG680. The implementation showed that ASPA used larger chip area (88 % of the chip) than SSDA (80 %). However its maximum possible frequency of operation (8.9 MHz) is more than that of SSDA (6.9 MHz). This is due to the complexity in SSDA design involved in finding parameters of the pulse.