Abstract: This thesis presents an FIR digital filter design, simulation and FPGA based implementation. Due to the importance of FIR filter in DSP, FIR filters can create transfer functions that have no equivalent in linear circuit technology. They can offer shape factor accuracy and stability equivalent to very high-order linear active filters that cannot be achieved in the analog domain. Unlike IIR (Infinite Impulse Response), the core of FIR is the MAC “Multiply & Accumulate” unit, the speed and the performance of the FIR depend on the MAC components, in which it consists of multiplier and adder unit. In this thesis a breeding of two types of multipliers “pipelining & LUT” with two types of adders “Ripple Carry and Carry look-ahead” which produces four design versions. These designs are introduced with their VHDL scripts, and a comparison had been made between them according to simulations of these designs using a merging between two major softwares “MATLAB & MODELSIM” in a process called co-simulation, which gives a real-time observing on the input & the output signals in analogue or digital approacheswithout writing a test-bench or what so ever. Results shows that FIR filter of 8- tabs, a resolution of 8-bit input data, and 8-bit coefficient, with MAC unit consists of pipelining multiplier with carry-look ahead adder offers the optimum speed “delay of 30ìs” depending on co-simulation results, and a midway of gates capacity “12k gates” depending on Xilinx ISE pack, therefore reasonable cost with reliable performance, while other designs serves the same objective but with lower speed 84ìs “MAC of Ripple Carry with pipelining” or high gate capacity 22k like “MAC of Carry Look Ahead with LUT multiplier”.