Abstract: During the last decade, smart cards have become a widespread digital device. Advantages of smart cards are, for instance, low development costs and thepossibility to obtain a high degree of stability and security. They are frequently used for sensitive applications like money withdrawal or identification systems. The secured identification mechanism of smart cards depends on protocol which can be built in optimized hardware by using a Hash function whereas the heart core for any Hash function is an encryption cipher. One of the most efficient ciphers is KASUMI block cipher which is not broken until now. Most of the identification systems nowadays need small size hardware ciphers, therefore a lot of researches went and are going towards building an optimized hardware implementation for cryptographic ciphers like KASUMI. In this research, optimized hardware implementation for KASUMI block cipher is implemented by using ACTEL FPGA technology. The main principle adopted to build this cipher is the reuse or iteration method in order to minimize the size of this cipher to a small one as possible. The proposed design uses one FO module, one FL module and one FI module to build the eight rounds of KASUMI block cipher depending on the reuse method and the strategy of iteration over a simplified rotational logic controlled by state machine. The design is implemented on ACTEL FUSION FPGA AFS600 evaluation board using VHDL as the programming language and the result obtained to implement this cipher is 1660 core cells which is equal to 12% of the total capacity of the FPGA core cells.