Programmable convolutional encoder using FPGA

Abstract: In future radio systems, flexible coding and decoding architectures will
be required. It can provide substantial improvement in bit error rates so that small, low power, inexpensive transmitters can be used in such applications as satellites and hand-held communication devices, so the implementing architectural flexibility with regard to low power issues is a challenging task. The flexible encoding platform in this thesis is a first step toward this envisioned decoder. It generates a wide class of codes, starting with convolutional codes. As an extension to this, turbo codes will be included in future by adding an interleaver. At this prototyping stage, the system is implemented on an FPGA. This thesis developed a Programmable Convolutional Encoder (PCE) using a Field Programmable Gate Array (FPGA). The implementation of the PCE is implemented using Xilinx Spartan-3A 1800A DSP starter platform (XC3SD1800A-4-FG676) hardware and Xilinx Integrated Software Environment (ISE) 9.2i. The target PCE is capable of coding a digital data stream with any one of 32 convolutional codes. The programmable feature of the encoder enables the user to the encoder parameters without changing the main design platform or using additional hardware. The encoder has a simple microprocessor interface, a register file for storage of code parameters, and a test circuit. The schematic design is used to model abstract behavior and to define relationships between building blocks. The ISE Project Navigator easy generates a The Hardware Description Language (VHDL) source codes and any other necessary file used in synthesis and implementation from schematic source file. Total equivalent gate count for design is 1,562 gates, where the design utilization capacity is less than 1% of the FPGA slices and LUTs, but it is around 4% and 6% of FPGA BUFGMUXs and bonded IOBs respectively. The experimental data reveals that the implemented encoder can deal with data rate as high as 44.5Mbps.