Abstract : The aim of this thesis is to design and implement Digital Down Converter (DDC) using Field Programmable Gate Array (FPGA) chip for input sampling frequency of 40 MHz and 25 KHz channel bandwidth. The Xilinx FPGA is chosen here with Virtex-II device to achieve this task for the DDC system implementation. The individual components of the DDC system are the mixer with its adder/subtractor and multiplier, Numerical Controlled Oscillator (NCO), and decimation filter. These components are software implemented using VHDL language, with the software called ModelSim version SE-EE 5.4a. The input data is chosen here with small additional noise about -78 dB and output data after multiplier about -84dB worst case of additional noise which depends on data resolution. A complex multiplier/mixer is an important part in DDC because of high speed need, so parallel tree multiplier is used. Four different types of NCO are used to design and implement the DDC systems with different methods to achieve different Spur Free Dynamic Range (SFDR) depending on resolution. Two designs are used the direct Sine Look-up Table (SLT) method, the third is two levels SLT method and the fourth is Xilinx core design previously introduced. Multirate technique is used for efficient FIR implementation by allowing filtering to be performed at much lower rate, which greatly reduces the filter order. A decimation FIR filter with Kaiser Window is used to have a low cost filter and can achieve an exact linear phase response with unconditionally stability. A Distributed Arithmetic (DA) realization is used to reduce multiplier effect. The proposed design of DDC is simulated by using ISE 4.1i and resulted in successful achievement of its design specification. The resulting performances depend on NCO design inverted in DDC. A great reduction in the required number of slices is achieved for the desired DDC when compared to that of Xilinx core.